Field of the Invention
This invention relates to a microprocessor system and, more particularly, to a microprocessor system having a central processing unit that employs an external memory containing a program counter.
Prior Art
The development of large-scale integrated circuits (LSI) has made possible the design of microprocessor systems which are capable of performing specialized computer functions. A microprocessor may comprise the control and processing portion of a small computer. Microprocessors, like all computer processors, can perform both arithmetic and logic functions in a bit-parallel manner under the direction of a stored program. Microprocessors, then, are inherently programmable. When placed in a system with peripheral memory circuits to provide the control program, and with input-and-output circuits, a microprocessor system is obtained which has a power of computation less than that of a minicomputer. As large scale integration technology advances, however, the power of computation of microprocessor systems approaches that of minicomputers.
Microprocessor systems generally derive their organization from the organizational and architectural concepts established from computers and minicomputers. The placement of a central processing unit, memory circuits, input-and-output circuits and miscellaneous support circuitry on a minimum number of integrated circuit chips inherently entails the employment of a small number of packages, which have a large number of external connectors or pins.
The typical prior art microprocessor architecture requires that a program counter be included in the central processing unit, and that this counter select the particular external memory to be addressed for retrieving program instruction codes. The use of a program counter in the CPU requires the use of a multiple-bus structure between the CPU and the memory. That is, at least one separate dedicated bus is employed for transferring data, and another dedicated bus for transferring addresses to the memory. The net result is that a larger number of pins are required on the CPU chip. Another approach in the prior art has been to employ a single bus between the CPU and an external memory, wherein data and addresses are time-multiplexed along the bus. This technique has a distinct disadvantage of requiring more complex circuitry, and a loss of process time for the multiplexing operation.